Design and Implementation of FPGA for Digital Channelization Processing

Electronic warfare receivers are required to possess a wide instantaneous bandwidth, exceptional demodulation sensitivity and frequency resolution, extensive dynamic range, and the ability to process multiple signals in parallel. Against this backdrop, channelized receivers have emerged as an ideal solution due to their unique performance advantages, making them well-suited to meet the demands of modern battlefield environments. Digital channelization is a method that employs encoding and decoding techniques to process digital communication signals, thereby enhancing transmission quality and reliability [1]. In recent years, with the continuous advancement of communication technologies and the expansion of application scenarios, the importance of digital channelization and digital filters in communication systems, the Internet of Things, satellite communications, and intelligent transportation has significantly increased [2].

FPGA, as a flexible and programmable hardware platform, provides an efficient means for implementing digital channelization algorithms. FPGA-based digital channelization techniques represent an effective signal processing approach capable of decomposing a broadband signal with substantial instantaneous bandwidth into multiple narrowband signals, which are then allocated to different channels. The number of channels is typically predetermined, such as 32-channel processing mentioned in this study.

Thamizharasan and Kasthuri [3] proposed an efficient FPGA-based digital down-conversion design tailored to software radio applications. Zhang et al. [4] introduced a design approach that incorporates undersampling and frequency estimation in channelization applications. Datta and Dutta [5] designed the efficient implementation of a half-band filter on the FPGA. Kim et al. [6] used digital down-conversion for equivalent time-domain signal sampling in complex periodic signals. Furthermore, Zhang et al. [7] presented an ultra-wideband digital back-end system for the QTT, employing a Polyphase Filter Bank (PFB) algorithm. Zhang et al. [8] investigated channelization techniques for radio astronomical wideband signals using oversampled PFBs. Liu et al. [9] proposed a frequency measurement approach for microwave signals over a wide frequency range, leveraging an optical frequency comb combined with a channelization method. Huiskamp et al. [10] introduced a method for reconstructing aliased frequency spectra by employing multiple sample rates. Song et al. [11] presented an optimized compressed spectrum sensing technique based on a multicoset sampler for multiband signals, approaching the sub-Nyquist boundary. Furthermore, Huang et al. [12] demonstrated parameter measurement for multiple exponentially damped sinusoids using sub-Nyquist sampling.

While these studies focus on the application of algorithms for digital processing, they lack validation and extension in practical engineering implementations. To address critical technological bottlenecks and reduce manufacturing costs, it is imperative to pursue independent development and domestically produced alternatives for core technologies. The FPGA design of the digital channelization receiver described in this study includes several key modules, namely the data preprocessing module, the Finite Impulse Response (FIR) filter bank module, the inverse FFT (IFFT) module, and the digital signal processing module. The data preprocessing module is responsible for introducing external signals into the system and performing integer-factor decimation on the input data, which reduces the sampling rate while transmitting the processed data to the FIR module. Subsequently, the FIR filter bank module processes the signals by filtering them according to their frequency characteristics and performing necessary spectrum shifting. Next, an IFFT module, implemented using butterfly operations, performs the 32-channel IFFT, converting signals from the frequency domain to the time domain. Finally, the digital signal processing module applies quantization and other processing steps to the output signals to meet specific output requirements. Through the integration and coordinated operation of these modules, the overall digital channelization workflow is achieved. This process effectively decomposes the original signal into multiple channels for parallel processing, ultimately accomplishing digital channelization.

Digital channelization is achieved through the reception of bandpass signals using FIR filters. During the channelization process, digital processing techniques such as FFT were employed to enable efficient and accurate signal reception and processing. When handling data sampled by the ADC, the data acquisition rate of the ADC differed from the processing rate of the receiver, necessitating the consideration of data buffering and processing during transmission.

To reduce the data rate obtained from the ADC, integer-factor decimation is commonly applied. Integer decimation refers to the process of resampling the original sequence $x(n)$ by selecting every $N$-th sample point (where $N$ is an integer), resulting in a new sequence $x_N(m)$ with a sampling rate $f_s^{\prime}=f_s / N$ [13]. This can be expressed as follows:

\[x_N(m) = x(mN)\]

Assuming the sampling rate of the original sequence is $f_s$, with a sampling interval of $T$, the Fourier transform of the original sequence is given by:

\[\begin{aligned} & \left.\mathrm{X}\left(\mathrm{e}^{j \varpi}\right)\right|_{\varpi=\Omega T}=\hat{X}_a(j \Omega)=\frac{1}{T} \sum_{k=-\infty}^{\infty} X_a\left(j \Omega-j \frac{2 \pi}{T} k\right)=\frac{1}{T} \sum_{k=-\infty}^{\infty} X_a\left(j \frac{ \varpi-2 \pi}{T} k\right)\end{aligned}\]

The sampling rate of the decimated sequence $x_N(m)$ became $f^{\prime}{ }_s=f_s / N$, with a corresponding sampling interval of $T^{\prime}=N T$. The Fourier transform of the sequence $x_N(m)$ can be expressed as follows:

\[\begin{aligned} & \left.\mathrm{X}\left(\mathrm{e}^{j \varpi^{\prime}}\right)\right|_{\varpi^{\prime}=\Omega T^{\prime}}=\hat{X}_a^{\prime}(j \Omega)=\frac{1}{T^{\prime}} \sum_{k=-\infty}^{\infty} X_a\left(j \Omega-j \frac{2 \pi}{T^{\prime}} k\right) =\frac{1}{N T} \sum_{k=-\infty}^{\infty} X_a\left(j \frac{\varpi^{\prime}-2 \pi}{T} k\right)\end{aligned}\]

It can be observed from these expressions that integer-factor decimation improves the frequency-domain resolution of the ADC signal. This enhanced resolution is advantageous for subsequent digital processing workflows [14].

Digital quadrature downconversion is a widely used technique in communication systems, primarily employed to enhance spectrum utilization. In communication scenarios, signals transmitted through the air are typically real-valued [15]. Upon reception, such signals must be demodulated to convert them into baseband frequencies. During this process, the signal is decomposed into two orthogonal components: the in-phase component (I) and the quadrature component (Q), collectively referred to as IQ components. The purpose of this transformation is to facilitate efficient signal processing and enable subsequent processors or demodulators to interpret and handle the signal more effectively. Through IQ components, the receiver is capable of extracting critical information from the original signal, ensuring accurate data transmission and processing [16]. Consequently, digital quadrature downconversion plays a pivotal role in modern communication systems by enabling higher spectrum efficiency and reliable data transmission.

Digital quadrature downconversion typically employs $\cos \left(\omega_0 n\right)$ and $-\sin \left(\omega_0 n\right)$ to perform frequency translation. The original input signal is multiplied by these transformation factors to convert the radio frequency (RF) signal into I and Q signals. A structural diagram of this process is illustrated in Figure 1.

A digital channelization receiver based on a polyphase filter structure was designed, with the core principle being the use of a parallel sampling digital structure featuring different frequency mixing coefficients to achieve channelization in the frequency domain, thereby generating baseband signals [17]. Compared to directly processing high-speed ADC data through multiplication with mixing factors, this approach imposes lower requirements on mixers, making it more resource-efficient and easier to implement [18]. However, the increase in the number of channels, with each channel requiring a unique mixing factor, leads to higher hardware resource consumption [19].

To address this challenge, a channelization structure based on polyphase filtering was adopted for signal processing. This structure performs exceptionally well when handling multi-channel inputs and effectively reduces hardware resource consumption. The structural diagram of a polyphase filter [20] is shown in Figure 2. By utilizing polyphase filters, the receiver achieves more efficient processing of input signals, improving system performance and scalability.

The FPGA module design for the digital channelization receiver comprises the following key components: the data preprocessing module, the filter bank module, the IFFT module, and the signal processing output module.

The data preprocessing module is responsible for converting serial input data into a parallel form, facilitating subsequent processing stages. The FIR filter bank module is then utilized to filter the input signals, eliminating noise and unwanted frequency components to enhance signal quality. The IFFT module performs the IFFT, converting frequency-domain signals back into the time domain for further processing. Finally, the signal processing output module applies necessary operations such as demodulation, decryption, or other signal processing algorithms [10].

Channel division can be categorized into uniform channelization and non-uniform channelization. In this design, a uniform channelization method was adopted for the filter bank design. The structural diagram of the system is shown in Figure 3.

Integer-factor decimation was achieved using serial-to-parallel conversion techniques to preprocess the acquired data. This technique allows high-speed serial data streams to be decomposed into multiple low-speed parallel data streams, thereby enabling data downsampling without any loss of information. This approach is particularly significant in digital signal processing as it facilitates the efficient management and handling of large data streams. The overall RTL framework for the FPGA design of digital channelization is illustrated in Figure 4.

To ensure the effective application of FIR filtering in subsequent stages, appropriate data preprocessing must be performed. The core objective of the preprocessing stage is to implement serial-to-parallel conversion, facilitating data rate reduction.

Integer-factor decimation was employed to achieve the downsampling of data acquired by the ADC. In FPGA implementations, this process is typically realized using serial-to-parallel conversion techniques [20]. The primary task of this module is to shift the ADC data and convert it into serial data with a specific bit width. During this process, due to the integer-factor relationship inherent in decimation, overlapping of output serial data occurs. For instance, if the output serial data has a bit width of 512 bits, there will be an overlap of 256 bits between consecutive segments. The workflow of the data preprocessing module is illustrated in Figure 5.

The core of implementing this process lies in the precise control of the flag bit, enabling the orderly shifting of input ADC data into registers to ultimately construct a complete 512-bit serial data stream. This sophisticated design not only optimizes the handling of high-speed data inputs but also fundamentally ensures the accuracy, integrity, and completeness of the data. Through this approach, the FPGA is able to effectively manage high-speed data streams from RF signals, providing a robust data foundation for subsequent signal processing and demodulation.

The RTL diagram of the data preprocessing module, as generated in Vivado, is shown in Figure 6.

From the perspective of hardware implementation, achieving an ideal sharp cutoff characteristic in filter design is challenging. In practical applications, a very narrow transition band significantly increases filter complexity, leading to a higher number of required multipliers and potentially extending filtering processing time. These factors considerably increase hardware resource consumption and reduce data processing rates [21].

To ensure that no critical information is missed, a filter bank with 50% overlap was employed for filtering operations. This design enhances the comprehensiveness of information capture, ensuring continuity and accuracy during signal monitoring and minimizing the risk of data loss or omissions. Additionally, the transition band of each filter was designed to be relatively wide. This approach effectively reduces the order of the FIR filters, simplifying the filter structure and significantly lowering computational complexity and resource utilization, thereby efficiently utilizing hardware resources.

By employing this filter bank design, hardware resources were utilized efficiently while maintaining system performance. Additionally, the approach ensures full coverage of all frequencies within the monitoring bandwidth. This method is widely adopted in digital signal processing, particularly in scenarios where efficient signal processing is required under limited hardware resources. Table 1 shows the channel allocation and filter numbers.

The bandpass filter bank was implemented by modulating a prototype low-pass filter with 192 taps. Based on the selected design parameter K=32, the number of phases P in each PFB can be calculated, with P=N/K. Thus, 192/32=6. Each phase filter coefficient was extended by inserting zeros, specifically two zeros between every coefficient, resulting in 12 coefficients for each phase filter.

In this PFB design, each coefficient of the prototype filter was reused in a specific pattern, with zero values inserted between repetitions of the coefficients. This approach not only conserves hardware resources but also enhances the flexibility and response speed of the filter. By processing input signals through these polyphase filters, uniform distribution of the data stream across all phases is ensured, enabling efficient frequency bandwidth utilization and signal reconstruction.

The data processing workflow demonstrates how input data is managed through these polyphase filters and how the processed data is combined to form the final output signal. In practical applications, this polyphase filter structure is commonly employed for efficient signal demodulation and bandwidth management, particularly in frequency-selective signal processing and communication systems. The implementation details and optimization strategies of each FIR filter significantly influence the overall performance and efficiency of the system. Figure 7 shows the filter structure.

When the ${{FIR}\_{STEP}}$ parameter was set to 12 and the number of filters was 32, each FIR filter contained 192 coefficients, with each coefficient occupying 16 bits. These coefficients were generated using the filterDesigner tool in MATLAB. The coefficients were divided into 32 groups, each containing 12 coefficients, with zero-padding applied between coefficients. The RTL implementation diagram of the FIR filter bank module is shown in Figure 8.

The required tap coefficients for each filter were not described individually. Instead, the FIR filters were designed in MATLAB, and their functions were generated. These tap functions were directly written into Verilog HDL files, serving as the tap sources for the FIR filter bank.

The IFFT is a critical technique used to convert frequency-domain signals back into the time domain. In the implementation of the IFFT, a practical approach involves first removing the complex conjugate of the signal, then performing a FFT, followed by taking the complex conjugate of the result and multiplying it by a coefficient $\left(\frac{1}{N}\right)$.

For processing ADC sampling data, PFBs were employed for filtering. This approach enables the simultaneous output of 32 filtered signals, achieving efficient parallel processing. The utilization of this filtering technique not only enhances the speed of data processing but also ensures the accuracy and quality of signal handling. To address the issue of excessive data throughput caused by serial input, a fully parallel IFFT operation based on radix-2 time-decimation was adopted. This design ensures efficient handling of high-speed data streams while maintaining the fidelity of the transformed signals, making it particularly suitable for high-performance digital signal processing applications. In this design, the IFFT module features 32 inputs and is tasked with executing 32-point parallel IFFT operations. By leveraging the properties of the FFT, a 32-point Inverse Discrete Fourier Transform (IDFT) can be decomposed into a series of smaller-scale IDFT computations. Specifically, a 32-point IDFT can be divided into two 16-point IDFTs. This decomposition process can be recursively continued until the original 32-point IDFT is reduced to 16 computations, each comprising 2-point IDFTs. This decomposition methodology significantly simplifies computational complexity and enhances operational efficiency. Based on this principle, Decimation-In-Time for the IFFT (DIT-IFFT) can be applied to the 32-channel data output from the filter bank. This approach enables efficient handling and analysis of the data, further optimizing the overall signal processing workflow. The RTL diagram of the 32-point parallel IFFT module is shown in Figure 9.

This module performs specific operations on the output data from the IFFT, focusing on the processing of odd-numbered channels. For the output data of the $n$-th odd channel, a multiplication operation by the $n$-th power of -1 is applied, where $n$ represents the output data of the $n$-th channel.

In digital quadrature demodulation, the exponential term in the product $e^{-j w_k M n}$ can be expressed as $(\cos k \pi-j \times \sin k \pi)^n$, where $F=\frac{K}{M}=2 ; k$ denotes the $k$-th phase result from the filter; and $n$ represents the output data of the $n$-th channel. This indicates that the data from the $n$-th channel undergoes a multiplication operation corresponding to (-1)$^{\mathrm{n}}$. Specifically, the data from odd-numbered channels are processed by $\times$ (-1), while the data from even-numbered channels remain unchanged. Following the operation, all signals are output together. In practical terms, the data from channels 0, 2, ..., 14 are left unaltered, while the data from channels 1, 3, ..., 15 are multiplied by (-1) before being output. The purpose of this operation is to adjust the channels to ensure correct processing or demodulation in subsequent stages. The RTL design of the digital signal processing module is shown in Figure 10.

The key tasks in the MATLAB simulation include generating the tap coefficients for the FIR filter bank and producing the signals required for the digital channelization receiver.

In this module, the FIR filter tap coefficients were generated based on the design requirements. These coefficients define the frequency response characteristics of the filters used for processing the input signals, including parameters such as filter type and cutoff frequency. The generation of these coefficients must consider the filter design specifications and performance criteria to meet the system requirements.

Additionally, MATLAB was employed to simulate the generation of analog-to-digital (AD) signals required for digital channelization. The ADC acquisition process was mimicked, and the data was exported into a text file. These data served as the ADC acquisition inputs during the digital channelization simulation.

To achieve efficient data processing, a uniform channelization strategy was selected, with the number of subchannels set to K = 32. To capture and analyze detailed information within the signal, an ADC sampling frequency of 512 MHz was adopted. Based on this sampling frequency and the number of subchannels, the bandwidth of each subchannel was precisely calculated to be 16 MHz, while the total processing bandwidth extended up to 32 MHz, ensuring broad signal coverage and high-resolution capability. To optimize signal quality, particularly during the filtering stage, a 192-tap low-pass filter was specifically designed. This filter plays a critical role in the digital channelization system, effectively eliminating high-frequency noise and interference to ensure accuracy and reliability during subsequent signal processing. This well-designed filtering scheme provides a robust foundation for the entire signal processing workflow. The Filter Designer tool in MATLAB was used to design the filter. The filter function was then exported and incorporated into the FIR module, where it served as the basis for FIR filter design.

Instead of using ADC for data acquisition, MATLAB was employed to simulate the acquisition process. In this simulation, ADC data was generated in MATLAB and an ADC sampling frequency of 512 MHz was set, with the carrier frequency of the signal to be captured set at 320 MHz and the simulated ADC sampling bandwidth set to 20 MHz.

Using MATLAB, a function was employed to generate a modulated signal centred around a carrier frequency of 320 MHz with a bandwidth of 20 MHz. This signal was then sampled at a frequency of 512 MHz, indicating that the signal was sampled 512 million times per second. Following the sampling process, the resulting digital signal was converted into binary data and saved to a text file for subsequent simulation. Figure 11 shows the amplitude-frequency spectrum.

The primary task of the data preprocessing module is to convert parallel AD data into a 512-bit serial data stream. This module plays a critical role in the signal processing system by transforming high-speed parallel data into a serial format that is easier to handle and transmit, thus facilitating subsequent signal processing stages.

In this module, parallel AD data, typically consisting of a series of samples acquired from the analog signal, was first received. The ADC data used in this simulation was generated by MATLAB, representing a radio-frequency signal. The data was directly read from the previously generated text file. Subsequently, the parallel data was converted into a 512-bit serial data stream. The simulation results of this module are presented in Figure 12.

The ${adc\_clk}$ signal serves as the clock signal used to control AD data acquisition. The ${output\_tvalid}$ flag is a status indicator that signifies the completion of the serial-to-parallel data conversion. The ${adc\_din}$ signal represents the input data from the ADC , while ${output\_tdata}$ refers to the converted data output after the serial-to-parallel transformation. In summary, when the ${adc\_clk}$ is triggered, AD data is input through ${adc\_din}$. After undergoing serial-to-parallel conversion, the data is output through ${output\_tdata}$ once the ${output\_tvalid}$ flag becomes active.

The primary function of the FIR filter bank module is to perform filtering and mixing operations on the input signal, removing components outside the predefined frequency range to ensure that the output signal meets specific requirements. Additionally, this module shifts the spectrum of the input signal to the baseband while generating the corresponding I and Q components. These operations provide essential preprocessing for the subsequent IFFT stage. Through precise filtering by the FIR filter bank, the processed signal can become cleaner and more aligned with the system requirements, thereby improving overall system performance. The simulation results of this module are shown in Figure 13.

${output\_data\_ i}$ [13] and ${output\_data\_q}$ [13] represent the I and Q components of the output from the 13$^{\text {th }}$ channel, respectively. The figure illustrates the output results of the 13$^{\text {th}}$ input signal after processing by the FIR filter bank. It can be observed that, after filtering, the output signal retains only the required 320 MHz component, while unwanted frequency components are effectively removed. This demonstrates that the FIR filter bank successfully filters out signals outside the specified range and shifts the spectrum of the desired signal to the baseband.

The primary function of the digital channelization receiver is to convert input signals with a large instantaneous bandwidth into output signals with smaller instantaneous bandwidths. This conversion process not only conserves communication resources and improves signal transmission efficiency but also ensures that the signals can be accurately reconstructed and decoded at the receiver end, enabling reliable communication and data transmission.

In this simulation, the input excitation signal was generated using MATLAB and saved as a TXT file to serve as the ADC-acquired data. The overall simulation results of the digital channelization receiver are shown in Figure 14. Figure 15 shows partial channel output results.

The signals processed by the system included the input ADC signal, marked as $adc\_in$. After processing, the system output 32 channels of serial data. The I components, representing the real part, were stored in $output\_data\_i$, while the Q components, representing the imaginary part, were stored in $output\_data\_q$. For different digital channels, specific output signals were identified as follows:

a) For the 11$^{\text{th}}$ channel, the I and Q components are represented by $output\_data\_i11$ and $output\_data\_q11$, respectively, corresponding to a channel bandwidth of 328 MHz to 344 MHz.

b) For the 12$^{\text{th}}$ channel, the I and Q components are represented by $output\_data\_i12$ and $output\_data\_q12$, respectively, corresponding to a channel bandwidth of 312 MHz to 328 MHz.

c) For the 13$^{\text{th}}$ channel, the I and Q components are represented by $output\_data\_i13$ and $output\_data\_q13$, respectively, corresponding to a channel bandwidth of 296 MHz to 312 MHz.

d) For the 14$^{\text{th}}$ channel, the I component is represented by $output\_data\_i14$, corresponding to a channel bandwidth of 280 MHz to 296 MHz.

e) For the 10$^{\text{th}}$ channel, the Q component is represented by $output\_data\_q10$, corresponding to a channel bandwidth of 344 MHz to 360 MHz.

Upon entering the digital channelization system, the input RF signal underwent a series of processing stages, including serial-to-parallel conversion, FIR filter bank processing, IFFT computation, and subsequent transformations. This sequence of operations transformed the original wideband RF signal into signals with narrower instantaneous bandwidths, enabling the receiving end to capture and analyze the transmitted signals more effectively. As shown in the results above, and based on the previously defined channel division, it is evident that the responses of the 11$^{\text{th}}$ and 13$^{\text{th}}$ channels were significantly stronger than those of other channels when the system processed signals acquired by the ADC. These simulation results confirm that the digital channelization receiver successfully completed the digital channelization process. The instantaneous bandwidth and sampling rate of the input signal were significantly reduced.

The digital channelization processing was tested on the FMQL45T900 FPGA evaluation board developed by Fudan Microelectronics. A setup with five ADC channels was implemented, capturing five intermediate-frequency signals. A single RF signal was generated using a signal generator, split into five parallel signals via a power splitter, and input into the five ADC channels. On the FPGA board, the processes of AD sampling, data preprocessing, FIR filtering, and IFFT transformation were completed to extract corresponding frequency information. These operations provide the foundation for subsequent Fourier transformations, frequency acquisition, phase extraction, and other processing tasks. The domestic FMQL45 series FPGA by Fudan Microelectronics is fully compatible with the ZYNQ 7045 series developed by Xilinx.

The FMQL45T900 integrates two ARM Cortex-A9 cores and a Kintex 7 FPGA. The FPGA’s programmable logic (PL) extends interfaces such as FMC, Ethernet, and I/O, while the processing system (PS) based on ARM supports extensions for networking, USB, and RS232 interfaces. The board is suitable for applications in image processing, vibration analysis, communication systems, radar front-end signal processing, and handheld device development. Figure 16 shows the test board. Figure 17 shows the workflow diagram for the digital channelization application.

$\bullet$ Number of channels: 5 parallel channels.

$\bullet$ ADC resolution: 16-bit resolution for low-speed channels.

$\bullet$ Maximum sampling rate: 250 Msps for low-speed channels.

$\bullet$ Acquisition clock: Supports both internal and external clocks.

$\bullet$ External trigger: Equipped with an external trigger interface.

$\bullet$ Synchronization precision: Better than 0.03 ns.

$\bullet$ Spurious-Free Dynamic Range (SFDR): Better than 85 dBFS for low-speed channels.

$\bullet$ Signal-to-Noise Ratio (SNR): Better than 70 dBFS for low-speed channels.

The validation of the proposed system was performed using a test setup built around the domestic FMQL45T900 FPGA from Fudan Microelectronics. Intermediate-frequency signals were sampled, and wideband signals were processed in parallel across multiple channels. Amplitude data were obtained using FFT, and frequency information was derived using a frequency estimation algorithm. These tests verified the accuracy and effectiveness of the digital channelization receiver.

The proposed design was implemented on the FMQL45T900 FPGA, and the logic resource utilization is summarized in Table 2.

The proposed method was compared with the approach presented by Zhang et al. [8] regarding area, frequency, and power consumption, as shown in Table 3.

It is evident from Table 2 that the proposed method reduces the required slice registers compared to the work by Zhang et al. [8]. Table 3 further illustrates that both power consumption and performance have been improved. Moreover, the proposed method demonstrates effective implementation on the domestic FMQL45T900 FPGA, providing a robust foundation for digital channelization processing in indigenous electronic, communication, and radar systems. This ensures independence from foreign chips, thereby mitigating risks associated with potential restrictions and delays in equipment development.

This study primarily demonstrates the successful implementation of digital channelization processing on a domestic FPGA. The digital channelization workflow was modeled and simulated using MATLAB, and each module was implemented on the FPGA. An application test board was constructed based on the domestic FMQL45T900 FPGA, and the correctness of frequency measurement data was verified, confirming the feasibility of the digital channelization approach and improving processing efficiency. By employing digital signal processing techniques, broadband signals were decomposed into multiple narrowband channels, enabling parallel signal processing and frequency-selective analysis. The validation on a domestic FPGA demonstrated engineering adaptability and feasibility for domestic applications, effectively mitigating risks associated with foreign export restrictions and ensuring no delays in equipment development and maintenance. In the future, the increasing demand for processing multiple narrowband signals within high-bandwidth reception will impose higher efficiency requirements on digital signal processing. Imaginary number digital channelization processing remains a promising research direction.